This commit is contained in:
Tomas Krejci 2024-05-27 02:08:16 +02:00
parent 1b20f3d49c
commit 7ff3652e29

View File

@ -25,7 +25,6 @@ class LT_ABC(IR):
def tx(self, tx1, tx2, tx3):
self.append(2400, 600)
bits = self.bits
v = tx3 & 0xff
v |= (tx2 & 0xff) << 8
@ -34,6 +33,7 @@ class LT_ABC(IR):
v = rbit32(v)
v = v >> 8
self.append(2400, 600)
for _ in range(bits):
self.append(1200 if v & 1 else 600, 600)
v >>= 1