up logging on rx module
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8163706f08
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@ -3,6 +3,7 @@
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from utime import ticks_us, ticks_diff
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from olt_lib.ir_rx import IR_RX
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import logging
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# Bit reverse a 32 bit value
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@ -24,16 +25,19 @@ class SONY_ABC(IR_RX): # Abstract base class
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self._addr = 0
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self._bits = 24
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self.logger = logging.getLogger(__name__)
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self.logger.debug("LT_RX_ABC init")
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def decode(self, _):
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try:
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nedges = self.edge # No. of edges detected
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self.verbose and print("nedges", nedges)
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self.logger.debug(f"nedges {nedges}")
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if nedges > 50:
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raise RuntimeError(self.OVERRUN)
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bits = (nedges - 2) // 2
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if nedges not in (58, 30, 50) or bits > self._bits:
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raise RuntimeError(self.BADBLOCK)
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self.verbose and print("SIRC {}bit".format(bits))
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self.logger.debug(f"RX LT {bits:X}bit")
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width = ticks_diff(self._times[1], self._times[0])
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if not 1800 < width < 3000: # 2.4ms leading mark for all valid data
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raise RuntimeError(self.BADSTART)
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