up logging on rx module

This commit is contained in:
Tomas Krejci 2024-05-30 01:13:12 +02:00
parent 8163706f08
commit 50dbb17dd5

View File

@ -3,6 +3,7 @@
from utime import ticks_us, ticks_diff
from olt_lib.ir_rx import IR_RX
import logging
# Bit reverse a 32 bit value
@ -24,16 +25,19 @@ class SONY_ABC(IR_RX): # Abstract base class
self._addr = 0
self._bits = 24
self.logger = logging.getLogger(__name__)
self.logger.debug("LT_RX_ABC init")
def decode(self, _):
try:
nedges = self.edge # No. of edges detected
self.verbose and print("nedges", nedges)
self.logger.debug(f"nedges {nedges}")
if nedges > 50:
raise RuntimeError(self.OVERRUN)
bits = (nedges - 2) // 2
if nedges not in (58, 30, 50) or bits > self._bits:
raise RuntimeError(self.BADBLOCK)
self.verbose and print("SIRC {}bit".format(bits))
self.logger.debug(f"RX LT {bits:X}bit")
width = ticks_diff(self._times[1], self._times[0])
if not 1800 < width < 3000: # 2.4ms leading mark for all valid data
raise RuntimeError(self.BADSTART)